36 "xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
38 MMI_LDC1(%[ftmp1], %[pixels], 0x00)
39 MMI_LDXC1(%[ftmp2], %[pixels], %[
stride], 0x00)
40 "punpcklbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t"
41 "punpckhbh %[ftmp4], %[ftmp1], %[ftmp0] \n\t"
42 "punpcklbh %[ftmp5], %[ftmp2], %[ftmp0] \n\t"
43 "punpckhbh %[ftmp6], %[ftmp2], %[ftmp0] \n\t"
44 MMI_SDC1(%[ftmp3], %[
block], 0x00)
45 MMI_SDC1(%[ftmp4], %[
block], 0x08)
46 MMI_SDC1(%[ftmp5], %[
block], 0x10)
47 MMI_SDC1(%[ftmp6], %[
block], 0x18)
48 PTR_ADDU "%[pixels], %[pixels], %[stride_x2] \n\t"
50 MMI_LDC1(%[ftmp1], %[pixels], 0x00)
51 MMI_LDXC1(%[ftmp2], %[pixels], %[
stride], 0x00)
52 "punpcklbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t"
53 "punpckhbh %[ftmp4], %[ftmp1], %[ftmp0] \n\t"
54 "punpcklbh %[ftmp5], %[ftmp2], %[ftmp0] \n\t"
55 "punpckhbh %[ftmp6], %[ftmp2], %[ftmp0] \n\t"
56 MMI_SDC1(%[ftmp3], %[
block], 0x20)
57 MMI_SDC1(%[ftmp4], %[
block], 0x28)
58 MMI_SDC1(%[ftmp5], %[
block], 0x30)
59 MMI_SDC1(%[ftmp6], %[
block], 0x38)
60 PTR_ADDU "%[pixels], %[pixels], %[stride_x2] \n\t"
62 MMI_LDC1(%[ftmp1], %[pixels], 0x00)
63 MMI_LDXC1(%[ftmp2], %[pixels], %[
stride], 0x00)
64 "punpcklbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t"
65 "punpckhbh %[ftmp4], %[ftmp1], %[ftmp0] \n\t"
66 "punpcklbh %[ftmp5], %[ftmp2], %[ftmp0] \n\t"
67 "punpckhbh %[ftmp6], %[ftmp2], %[ftmp0] \n\t"
68 MMI_SDC1(%[ftmp3], %[
block], 0x40)
69 MMI_SDC1(%[ftmp4], %[
block], 0x48)
70 MMI_SDC1(%[ftmp5], %[
block], 0x50)
71 MMI_SDC1(%[ftmp6], %[
block], 0x58)
72 PTR_ADDU "%[pixels], %[pixels], %[stride_x2] \n\t"
74 MMI_LDC1(%[ftmp1], %[pixels], 0x00)
75 MMI_LDXC1(%[ftmp2], %[pixels], %[
stride], 0x00)
76 "punpcklbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t"
77 "punpckhbh %[ftmp4], %[ftmp1], %[ftmp0] \n\t"
78 "punpcklbh %[ftmp5], %[ftmp2], %[ftmp0] \n\t"
79 "punpckhbh %[ftmp6], %[ftmp2], %[ftmp0] \n\t"
80 MMI_SDC1(%[ftmp3], %[
block], 0x60)
81 MMI_SDC1(%[ftmp4], %[
block], 0x68)
82 MMI_SDC1(%[ftmp5], %[
block], 0x70)
83 MMI_SDC1(%[ftmp6], %[
block], 0x78)
84 : [ftmp0]
"=&f"(ftmp[0]), [ftmp1]
"=&f"(ftmp[1]),
85 [ftmp2]
"=&f"(ftmp[2]), [ftmp3]
"=&f"(ftmp[3]),
86 [ftmp4]
"=&f"(ftmp[4]), [ftmp5]
"=&f"(ftmp[5]),
87 [ftmp6]
"=&f"(ftmp[6]),
105 "li %[tmp0], 0x08 \n\t"
106 "xor %[ftmp4], %[ftmp4], %[ftmp4] \n\t"
108 MMI_LDC1(%[ftmp0], %[
src1], 0x00)
109 "or %[ftmp1], %[ftmp0], %[ftmp0] \n\t"
110 MMI_LDC1(%[ftmp2], %[src2], 0x00)
111 "or %[ftmp3], %[ftmp2], %[ftmp2] \n\t"
112 "punpcklbh %[ftmp0], %[ftmp0], %[ftmp4] \n\t"
113 "punpckhbh %[ftmp1], %[ftmp1], %[ftmp4] \n\t"
114 "punpcklbh %[ftmp2], %[ftmp2], %[ftmp4] \n\t"
115 "punpckhbh %[ftmp3], %[ftmp3], %[ftmp4] \n\t"
116 "psubh %[ftmp0], %[ftmp0], %[ftmp2] \n\t"
117 "psubh %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
118 MMI_SDC1(%[ftmp0], %[
block], 0x00)
119 MMI_SDC1(%[ftmp1], %[
block], 0x08)
120 PTR_ADDI "%[tmp0], %[tmp0], -0x01 \n\t"
121 PTR_ADDIU "%[block], %[block], 0x10 \n\t"
122 PTR_ADDU "%[src1], %[src1], %[stride] \n\t"
123 PTR_ADDU "%[src2], %[src2], %[stride] \n\t"
124 "bgtz %[tmp0], 1b \n\t"
125 : [ftmp0]
"=&f"(ftmp[0]), [ftmp1]
"=&f"(ftmp[1]),
126 [ftmp2]
"=&f"(ftmp[2]), [ftmp3]
"=&f"(ftmp[3]),
127 [ftmp4]
"=&f"(ftmp[4]),
MIPS assembly defines from sys/asm.h but rewritten for use with C inline assembly (rather than from w...
__asm__(".macro parse_r var r\n\t" "\\var = -1\n\t" _IFC_REG(0) _IFC_REG(1) _IFC_REG(2) _IFC_REG(3) _IFC_REG(4) _IFC_REG(5) _IFC_REG(6) _IFC_REG(7) _IFC_REG(8) _IFC_REG(9) _IFC_REG(10) _IFC_REG(11) _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15) _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19) _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23) _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27) _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31) ".iflt \\var\n\t" ".error \"Unable to parse register name \\r\"\n\t" ".endif\n\t" ".endm")
void ff_diff_pixels_mmi(int16_t *av_restrict block, const uint8_t *src1, const uint8_t *src2, ptrdiff_t stride)
void ff_get_pixels_8_mmi(int16_t *av_restrict block, const uint8_t *pixels, ptrdiff_t stride)